This invention relates to semiconductor devices and, more particularly, to semiconductor power devices and methods for fabricating such devices.
Power switching devices are devices of choice for handling large currents and large voltages. These devices, including bipolar transistors, field effect transistors, thyristors and diodes are used in a wide variety of power applications. Of these, devices which perform switching operations based on field effect principles are preferred when it is important to provide fast switching speeds and low current draw during switching operations.
In a conventional power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device it is desirable to minimize the on-resistance in order to reduce the power consumed while the device is in a conducting state. Although the resistance can, in principle, be reduced by increasing the dopant density in the various semiconductor layers, this may adversely affect device operation by, for example, allowing operation of parasitic devices, reducing forward blocking voltage or reducing the reverse bias breakdown voltage of the device.
In this regard, prior efforts to provide improved device performance have been of limited success. See, for example, U.S. Pat. No. 5,216,275 which discloses so called xe2x80x9csuper junctionxe2x80x9d devices. These comprise composite buffer layers formed with adjoining sublayers of semiconductor material having alternating conductivity types. Such structures, while in principle capable of providing significant improvement in performance, are of limited application due to inherent difficulties relating to control of dopant outdiffusion, particularly as the thickness of the sublayers decreases. The practical maximum electric field achievable in a super junction device is on the order of 2xc3x97105 V/cm and this limits the breakdown voltage of the device.
It is desirable to provide an improved semiconductor device that is not subject to such manufacturing limitations and which exhibits the combination of a higher breakdown voltage and a lower on-resistance. In U.S. Ser. No. 09/981,583, incorporated herein by reference, I have taught the application of bias electrodes, also termed charge electrodes, to realize such a device. Summarily, my inclusion of bias electrodes enables modification of the electric field in significant conduction regions, e.g., drift regions, of a semiconductor device.
The embodiments disclosed in Ser. No. 09/981,583 are applicable to the wide variety of power devices and specific designs are provided therein. It is now recognized that, with the application of bias electrodes to lateral devices, additional improvements in designs and manufacturing techniques are desirable to further improve the performance and commercial value of these power products.
According to the invention, an embodiment of a lateral transistor device includes a lightly doped layer of semiconductor material having first and second more heavily doped regions of a first conductivity type formed along a surface. A third region of a second conductivity type is between the first and second regions and a lightly doped region of the first conductivity type is between the second and third regions. A control electrode is positioned to enable conduction through the third region and a biasing electrode structure is positioned along the third region to alter the electric field in the third region.
In another embodiment a lateral transistor device is formed with a lightly doped layer of semiconductor material having a first more heavily doped region of a first conductivity type formed therein. A second more heavily doped region of the first conductivity type is formed in an opening extending from a surface of the layer into the layer. A third region of a second conductivity type is between the first and second regions. In an associated method a lightly doped layer of semiconductor material is formed with a first more heavily doped region of a first conductivity type. An opening is provided, extending from a surface of the layer into the layer and a second more heavily doped region of the first conductivity type is formed in the opening. A third region of a second conductivity type is formed between the first and second regions.
Another method of forming a lateral transistor device includes forming a lightly doped layer of semiconductor material having first and second more heavily doped regions of a first conductivity type formed along a surface and providing a third region of a second conductivity type between the first and second regions. A lightly doped region of the first conductivity type is formed between the second and third regions and a control electrode is positioned to enable conduction through the third region. A biasing electrode structure is positioned along the third region to alter the electric field in the third region. According to one embodiment of the invention the biasing electrode structure is positioned in a trench along the third region to control the electric field intensity in the third region.
A method of operating a lateral transistor device is also provided. Current is initiated through at least one of the device semiconductor junctions. Bias electrodes are operated to control field intensity in a drift region of the device during current conduction. In one embodiment the conduction is initiated in accord with field effect principles.